1. Field of the Invention
The present invention relates to a semiconductor device comprising: a chip including individually independent power supply wirings for providing power supply voltage to a plurality of output circuits, and power supply pads each connected to the power supply wiring; a substrate on which the chip is to be mounted and including a plurality of external power supply terminals, each of which is to be connected with each of the power supply pad.
2. Description of Related Art
FIG. 1 is a schematic diagram of a semiconductor chip. Semiconductor chip 2 is mounted on substrate 1 and has center pad 3 on its the central part. A multitude of balls 4 are disposed on substrate 1 at both sides of center pad 3. Center pad 3 of semiconductor chip 2 is connected to solid wirings (not shown) etc. of substrate 1. The connection from center pad 3 of semiconductor chip 2 to the solid wirings of substrate 1 is performed through a bonding process or by lead wires. The solid wirings on substrate 1 are connected to balls 4. Balls 4 that correspond to respective signals and power supplies are determined by a standard such as JEDEC (Joint Electronic Device-Electronic Industrial Association).
FIG. 2 is a detailed view of portion 5 in FIG. 1 of semiconductor chip 2; and FIG. 3 is an enlarged view of FIG. 2. DQ output circuit 11, DQS output circuit 12, DQSB output circuit 13, compensation capacity 14, and ESD (Electrostatic Discharge) element 15 are connected with in-chip output VDDQ power supply wiring 16 and in-chip output VSSQ power supply wiring 17, which are lower resistance wirings. DQ output circuit 11 is a circuit for outputting output signal DQ. DQS output circuit 12 is a circuit for outputting data strobe signal DQS. DQSB output circuit 13 is a circuit for outputting data strobe signal DQSB which is an inverted signal of data strobe signal DQS. Data strobe signals DQS and DQSB function as a reference clock for output signal DQ. That is, data strobe signals DQS and DQSB are complementary signals. A data strobe output circuit comprised of the DQS output circuit and the DQSB output circuit is an output circuit for outputting the complementary signals. Compensation capacity 14 serves to suppress fluctuations of the voltages in in-chip output VDDQ power supply wiring 16 and in in-chip output VSSQ power supply wiring 17. ESD element 15 is an element for electrostatic protection. In-chip output VDDQ power supply wiring 16 and in-chip output VSSQ power supply wiring 17 are wirings each providing high-level power supply voltage VDDQ and low-level power supply voltage VSSQ to DQ output circuit 11, DQS output circuit 12, and DQSB output circuit 13. DQ output circuit 11, DQS output circuit 12 and DQSB output circuit 13 have output signal lines that are connected to respective output circuit pads 21, 22, and 23, and are further connected to the corresponding solid wirings on substrate 1. Although not shown in the FIGS. 2 and 3, the solid wiring is connected to corresponding ball 4 on substrate 1. In-chip output VDDQ power supply wiring 16 is connected to power supply pads 24a to 24e on chip 2, and in-chip output VSSQ power supply wiring 17 is connected to power supply pads 25a to 25e on chip 2. Connections from power supply pads 24a, 24b, 24c, 24d, and 24e to respective VDDQ power supply balls 31, 42, 42, 42 and 34 on substrate 1, and connections from power supply pads 25a, 25b, 25c, 25d, and 25e to respective VSSQ power supply balls 41, 32, 32, 43, and 43 on substrate 1 are performed through bonding (a broken lines in FIGS. 2 and 3) etc. between these power supply pads and the solid wirings on substrate 1. To be precise, the wirings (broken lines in FIGS. 2 and 3) that extend on the substrate from the power supply balls disposed on substrate 1 are metallized wirings and the wirings (broken lines in FIGS. 2 and 3) on center pad 3 are bonding wires. The solid wirings are connected to VDDQ power supply balls 31, 34, and 42 and VSSQ power supply balls 32, 41, and 43 on substrate 1. Power supply voltage VDDQ is supplied from VDDQ power supply balls 31, 34, and 42 to DQ output circuit 11, DQS output circuit 12, and DQSB output circuit 13 through VDDQ power supply pads 24a to 24e and in-chip output VDDQ power supply wiring 16. Power supply voltage VSSQ is supplied from VSSQ power supply balls 32, 41, and 43 to DQ output circuit 11, DQS output circuit 12, and DQSB output circuit 13 through VSSQ power supply pads 25a to 25e and in-chip output VSSQ power supply wiring 17. It is to be noted that although signal wirings from output circuit pads 21, 22, and 23 of respective DQ output circuit 11, DQS output circuit 12, and DQSB output circuit 13 are also connected with balls 4 on substrate 1, the illustration of the signal wirings is omitted in FIGS. 2 and 3.
FIG. 4 illustrates circuit diagrams of DQ output circuit 11, DQS output circuit 12, and DQSB output circuit 13. In FIG. 4, although only the configuration of DQS output circuit 12 is shown, DQSB output circuit 13 and DQ output circuit 11 have similar configurations to that of DQS output circuit 12. DQ output circuits 11 take in data Data<n>R and Data<n>F stored in memory (not shown) in synchronization with clock LCLKOE and serially outputs data signals DQ0, DQ1, . . . , DQn from internally operating power supplies VDD and VSS as external output power supplies VDDQ and VSSQ. In this case, data Data<n>R is output in synchronization with the rise of clock LCLKOE and Data<n>F is output in synchronization with the fall of clock LCLKOE. Signals DQS and DQSB are generated by a circuit (not shown) in response to a read command from the outside, and are output from DQS output circuit 12 and DQSB output circuit 13, respectively. Signals DQSB and DQS have opposite phases. Although DQ output circuit 11, DQS output circuit 12, and DQSB output circuit 13 have the same configuration, a skew in input timing of clock LCLKOE is generated due to the difference in the positions of the circuits, which causes a timing difference (tDQSQ) of clock LCLKOE (FIG. 5A). In FIG. 4, since the timing at which clock LCLKOE is input into DQS circuit 12 and DQSB output circuit 13 is later than the timing at which it is input into DQ output circuit 11, the timing difference (tDQSQ) of output signals DQS and DQSB with respect to output signal DQ1 is at a maximum.
The reason why power supply noise is generated will be described with reference to waveform diagrams of output signals DQ, DQS, and DQSB shown in FIGS. 5A and 5B. While output signals DQS and DQSB always operate in opposite phases, output signal DQ changes depending on the data pattern. When the data patterns of output signals DQ do not change, power supply noise will not be generated in output circuits 11, 12, and 13. For example, when the patterns of output signals DQ change from a high level to a low level all together (FIG. 5A), power supply voltage VSSQ rises. At this time, DQS output circuit 12 and DQSB output circuit 13 operate with a time delay of tDQSQ from output circuit 11 that outputs DQ1 due to the positional relationships of output circuits 12 and 13 with respect to output circuit 11. For this reason, under the influence of the power supply noise due to the rise of power supply voltage VSSQ, a delay in the fall of output signal DQSB that is in phase with output signal DQ takes place resulting in an increase of the value of Vox. Conversely, when output signals DQ change from a low level to a high level, power supply noise is also generated due to the fall of power supply voltage VDDQ and the value of Vox is decreased due to the high level power supply voltage. Vox is an electric potential when output signals DQS and DQSB cross each other. An ideal value of Vox is (VDDQ−VSSQ)/2. The value of Vox has a range that is determined by a standard, and a value outside that range is problematic.
FIGS. 6 and 7 show paths along which power supply noise propagates. FIG. 6 illustrates the manner in which the power supply noise generated in output circuit 11 for outputting DQ1 (indicated by a star mark in FIGS. 6 and 7) propagates to DQS output circuit 12 and DQSB output circuit 13 via in-chip output VDDQ power supply wiring 16 and in-chip output VSSQ power supply wiring 17. Since in-chip output VDDQ power supply wiring 16 and in-chip output VSSQ power supply wiring 17 are made of a low resistance wire, power supply noise readily propagates to DQS output circuit 12 and DQSB output circuit 13 via in-chip output VDDQ power supply wiring 16 and in-chip output VSSQ power supply wiring 17. FIG. 7 illustrates the manner in which the power supply noise generated in output circuit 11 for outputting DQ1 propagates by way of the wires on substrate 1. Since DQS output circuit 12, DQSB output circuit 13 and DQ output circuit 11 have VSSQ power supply pads (25b and 25c) in common, power supply noise propagates from DQ output circuit 11 to DQS output circuit 12 and DQSB output circuit 13 via the wires and VSSQ power supply pads 25b and 25c. Specifically, in center pad 3 (surrounded by the broken line in FIGS. 6 and 7) and near the boundary between substrate 1 and center pad region 3, there are two bonding wires that are branched from the metallized wiring on substrate 1 and that are connected to respective VSSQ power supply pads (25b and 25c). Even if the VSSQ power supply ball has the capability to absorb noise, shorting or branching power supply lines in the vicinity of respective VSSQ power supply pads (25b and 25c) can result in the sharing of a low impedance noise at the vicinities of the circuit which is a noise source. The fact that the lengths of metallized wirings on substrate 1 are longer than the length of bonded wires is also a factor that explains why the above described phenomenon is accelerated.
As described above, there are two paths along which power supply noise generated by DQ output circuit 11 propagates to DQS output circuit 12 and DQSB output circuit 13.
JP11-163032A discloses, regarding a method of separating power supplies for circuit blocks in a semiconductor memory, a technique of searching for an optimum combination from among multiple combinations of the circuit blocks, but it fails to describe a configuration for reducing the generated power supply noise.